Sustav za povezivanje i udaljeno ispitivanje procesora FRISC izvedenog u programabilnoj logici

Živec, Tomislav

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master's thesis

Sustav za povezivanje i udaljeno ispitivanje procesora FRISC izvedenog u programabilnoj logici

Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2018. urn:nbn:hr:168:649278

Živec, Tomislav

University of Zagreb
Faculty of Electrical Engineering and Computing

Cite this document

APA 6th Edition

Živec, T. (2018). Sustav za povezivanje i udaljeno ispitivanje procesora FRISC izvedenog u programabilnoj logici (Master's thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:649278

MLA 8th Edition

Živec, Tomislav. "Sustav za povezivanje i udaljeno ispitivanje procesora FRISC izvedenog u programabilnoj logici." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2018. https://urn.nsk.hr/urn:nbn:hr:168:649278

Chicago 17th Edition

Harvard

Živec, T. (2018). 'Sustav za povezivanje i udaljeno ispitivanje procesora FRISC izvedenog u programabilnoj logici', Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 19 November 2024, https://urn.nsk.hr/urn:nbn:hr:168:649278

Vancouver

Živec T. Sustav za povezivanje i udaljeno ispitivanje procesora FRISC izvedenog u programabilnoj logici [Master's thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2018 [cited 2024 November 19] Available at: https://urn.nsk.hr/urn:nbn:hr:168:649278

IEEE

T. Živec, "Sustav za povezivanje i udaljeno ispitivanje procesora FRISC izvedenog u programabilnoj logici", Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2018. Available at: https://urn.nsk.hr/urn:nbn:hr:168:649278

Cite this item: https://urn.nsk.hr/urn:nbn:hr:168:649278

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Metadata

Title	Sustav za povezivanje i udaljeno ispitivanje procesora FRISC izvedenog u programabilnoj logici
Title (english)	Remote debugging system for FRISC processor implemented in FPGA
Author	Tomislav Živec
Mentor	Mario Kovač (mentor)
Committee member	Mario Kovač (predsjednik povjerenstva)
Committee member	Josip Knezović (član povjerenstva)
Committee member	Daniel Hofman (član povjerenstva)
Granter	University of Zagreb Faculty of Electrical Engineering and Computing Zagreb
Defense date and country	2018-07-03, Croatia
Scientific / art field, discipline and subdiscipline	TECHNICAL SCIENCES Computing
Abstract	Procesor FRISC izveden u programabilnoj logici nadograđen je Control and Debugging Unit modulom za kontrolu i udaljeno ispitivanje stanja procesora. CDU modul implementira slave stranu AXI-lite protokola za komunikaciju posebno dizajniranim automatom stanja, omogućava obradu naredaba za upravljanje radom FRISC-a te dohvat stanja njegovih registara. Udaljeno ispitivanje i upravljanje procesorom ostvaruje se upisivanjem odgovarajućih bitova u upravljački registar CDU modula što je demonstrirano posebno dizajniranom aplikacijom koja parsira naredbe poslane serijskom vezom preko UART-a i pomoću izvedenog sučelja ih prevodi u upravljačke riječi za CDU modul.
Abstract (english)	The FRISC processor, implemented in programmable logic, has been upgraded with the Control and Debugging Unit module for controlling and remote processor debugging. The CDU module implements slave side of the AXI-lite communication protocol with a specially designed state machine, enables processing of FRISC operation management commands and fetching the status of its registers. The remote debugging and processor management is accomplished by entering the corresponding bits into the control register of the CDU module as demonstrated by a specially designed application that parses the commands sent over serial port (UART) and translates them into control words for the CDU module using the derived interface.
Keywords
Keywords (english)
Language	croatian
URN:NBN	urn:nbn:hr:168:649278
Study programme	Title: Computing Study programme type: university Study level: graduate Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
Type of resource	Text
File origin	Born digital
Access conditions	Closed access
Terms of use
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Repository	FER Repository
Created on	2019-03-14 02:26:10